(1) Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a semiconductor non-volatile memory device, such as an EEPROM (Electrically Erasable and Programmable Read Only Memory) device or an EAROM (Electrically Alterable Read Only Memory) device which uses a floating-gate structure and which is used, for example, in an electronic computer.
(2) Description of the Prior Art
As illustrated in FIG. 1, in a conventional semiconductor nonvolatile memory device, wherein each of the memory cell transistors comprises a semiconductor substrate 1, a first impurity doped region 2 which is a source region, a second impurity doped region 3 which is a drain region, a floating gate 4 and a control gate 5. In FIG. 1, insulation films formed between the semiconductor substrate 1 and the floating gate 4 and formed at other portions and some other parts are omitted for the sake of simplicity.
In the memory cell transistor of FIG. 1, programming or write-in of information is achieved by simultaneously applying a predetermined bias voltage between the source region 2 and the drain region 3 and a high voltage, for example 20 V, to the control gate 5. Hot electrons are generated in the vicinity of the edge portion of the drain region 3 facing the channel region due to the avalanche break down and are injected into the floating gate 4 as illustrated by arrows in FIG. 1, resulting in an upward shift in the threshold voltage. Thus, only the operation in the enhancement mode is guaranteed.
After the above-mentioned write-in of information is achieved, electrical erasure can be attained by simultaneously applying the potential of 0 V to the source region 2 and the drain region 3 and a very high potential voltage, for example 30 V, to the control gate 5. Electrons stored in the floating gate 4 are injected into the control gate 5 by tunnel injection and are removed from the floating gate 4, so that the erasure of information is achieved. This tunnel injection is performed by Fowler-Nordheim emission.
When the above-mentioned erasure is effected, if too many electrons are removed from the floating gate 4, there occurs a condition which is as if positive holes were stored in the floating gate 4. Therefore, the memory cell transistor of FIG. 1 operates in the depletion mode, so that a drain source current flows even if the memory cell transistor is not selected, i.e., even if the gate potential is zero.
In order to solve such a problem, there is proposed the memory cell transistor of FIG. 2. In the memory cell transistor of FIG. 2, a part of a control gate 5, which is designated by the reference number 5', is formed directly on the channel region of the substrate 1 through an insulation layer formed therebetween (not shown in the drawing), so that a part of the channel region, on which is formed the part of the control gate 5, can be turned on and off directly by the control gate 5. The other portions are the same as those of FIG. 1 and are designated by the same reference numbers. In the structure of FIG. 2, even if a part of the channel region existing under the floating gate 4 operates in the depletion mode, the whole channel region between the source region 2 and the drain region 3 is controlled only by the control gate 5.
As illustrated in FIG. 3, in a process for manufacturing the memory device using the memory cell transistor of FIG. 2, the control gate and the floating gate are formed by trimming conductive layers 7 and 8 which are formed on the semiconductor substrate 1, by the photolithographic technique using a photoetching mask 9. After forming the control gate 5 and the floating gate 4, the source electrode 2 and the drain electrode 3 are formed, for example, by thermal diffusion.
However, the structure of FIG. 2 has a disadvantage in that it is necessary to adjust the position of the photoetching mask 9 very precisely when the trimming or the patterning of the control gate 5 is effected in the manufacturing process of the memory cell transistor. This is because, if the position of the photoetching mask 9 deviates, for example, in a direction illustrated by an arrow A from a predetermined normal position 9 to a position 9', then both the capacitance between the control gate 5 and the floating gate 4 and the capacitance between the floating gate 4 and the substrate 1 become larger. However, the area of the control gate 5, which faces the channel region and which is used for controlling the turning on and off of the channel region, becomes smaller than the predetermined value. Therefore such a deviation of the position of the photoetching mask causes dispersion of the electric characteristics of the memory cell transistors.
As illustrated in FIG. 4, in a semiconductor memory device using such memory cell transistors, the memory cell transistors Q.sub.m,n, Q.sub.m,n+1, Q.sub.m+1,n, Q.sub.m+1,n+1, . . . are usually arranged in a matrix. Each of the memory cell transistors is disposed at an intersection of one of the word lines WL.sub.n, WL.sub.n+1, . . . and one of bit lines BL.sub.m, BL.sub.m+1 , . . . The control gate of each of the memory cell transistors is connected to one of the word lines WL.sub.n, WL.sub.n+1, . . . , and, the drain electrode and the source electrode thereof are connected to one of the bit lines BL.sub.m, BL.sub.m+1, . . . and a voltage source V.sub.ss, for example ground, respectively.
FIG. 5 illustrates a cross section of a pair of memory cell transistors, for example the memory cell transistors Q.sub.m,n and Q.sub.m,n+1 of FIG. 4, which have a common drain electrode 3 connected to the bit line, for example, BL.sub.m. In the structure of FIG. 5, if the photoetching mask (not shown in the drawing) deviates in a direction shown by an arrow B from the predetermined normal position, then both the capacitance between the control gate 5 and the floating gate 4 and the capacitance between the floating gate 4 and the substrate 1 of the transistor Q.sub.m,n become larger than the predetermined normal value. However, the corresponding capacitances of the transistor Q.sub.m,n+1 become smaller than the predetermined normal value. In this case, the area 5' of the control gate 5 directly facing the channel region of the transistor Q.sub.m,n becomes smaller than the predetermined normal value, but the area 5' of the transistor Q.sub.m,n+1 becomes larger than the predetermined normal value. Therefore, the electric characteristics of both transistors Q.sub.m,n and Q.sub.m,n+1 change in reverse directions with each other, so that the dispersion of the electric characteristics of the memory cell transistors becomes very large.